The present invention relates generally to a method for forming fine patterns in a semiconductor device, and more particularly, to a method for forming a very fine lined pattern in a semiconductor device, in which the minimum geometries are below the resolution limits of the photolithographic equipment employed to form the pattern.
The scale of integration of semiconductor devices has been progressively increasing at a rapid rate, thereby necessitating commensurate reduction of the geometries of the photolithographically-formed patterns which define the various device features (e.g., MOS transistor gates) thereof. Thus, increasingly sophisticated pattern definition technologies have been required as the critical geometries have shrunk from the 6 .mu.m geometries of the 1970s to the submicron geometries of the 1980s to the deep submicron geometries of the 1990s. In this connection, the resolution limits of the optical wafer steppers employed in the photolithographic process has been advanced from 436 nm (g-line) to 365 nm (i-line), thereby enabling the formation of patterns with 0.4 .mu.m minimum feature sizes.
FIG. 1 illustrates a conventional method for forming a pattern in a semiconductor device. More particularly, a photoresist layer 25 is deposited on a layer 22 to be patterned which is formed on a substrate 21. Then, a mask (not shown) having the desired pattern is used to selectively expose the photoresist layer 25, which is then developed, to thereby form a photoresist pattern 25. Then, the layer 22 is patterned using the photoresist pattern 25 as an etching mask.
FIGS. 2-6 illustrate successive steps of a method for forming a capacitor storage electrode of a semiconductor memory device, in which the conventional method of forming a fine lined pattern, using an i-line stepper, is employed.
With reference now to FIG. 2, there can be seen a semiconductor memory device which includes transistors each having a gate 3 and source/drain regions 4 formed in a semiconductor substrate 1 which is divided into isolation and active regions by field oxide layers 2, with the gates 3 of the transistors being insulated from the substrate 1 by an insulating layer 5 (e.g., gate oxide layer). An interlayer insulating layer 6 is formed on the entire surface of the resultant structure, and an insulating material, e.g., a nitride, is deposited on the interlayer insulating layer 6, thereby forming an etch-blocking layer 7. An insulating layer 8 is formed on the etch-blocking layer 7.
With reference now to FIG. 3, a photoresist layer 11 is deposited on the insulating layer 8, and then patterned by a photolithographic process, to thereby form a photoresist pattern 11. The, contact holes 9 extending through the layers 6, 7, and 8 to the source/drain regions 4 are formed by anisotropically etching the layers 6, 7, and 8, using the photoresist pattern 11 as an etching mask.
With reference now to FIG. 4, the photoresist pattern 11 is removed and a conductive material is then deposited on the entire surface of the resultant structure, including the surface portions defining the contact holes 9, to thereby form a conductive layer 10.
With reference now to FIG. 5, a photoresist layer 12 is deposited on the surface of the conductive layer 10, and then patterned by standard photolithographic techniques, in order to thereby form a photoresist pattern 12.
With reference now to FIG. 6, the conductive layer 10 is patterned by means of an anisotropic etching process, using the photoresist pattern 12 as an etching mask, in order to thereby form separate storage electrodes 10'. Thereafter, the insulating layer 8 is removed by means of a wet etching process. The resultant spacing A between the adjacent storage electrodes 10' is approximately 0.4 .mu.m, when an i-line stepper is used in patterning the photoresist layer 12.
Thus, with the conventional method, even when the highest resolution stepper (an i-line stepper) is utilized, the minimum spacing A between adjacent features of the photoresist pattern used as an etching mask in forming a fine lined pattern in the semiconductor device, e.g., the storage electrodes of the capacitors of the memory cells of a dynamic random access memory (DRAM), is approximately 0.4 .mu.m. This design rule constraint imposes an upper limit on the achievable density of the semiconductor memory device. Thus, in order to increase the cell packing density beyond that which is possible using the presently available fine pattern formation techniques, it is necessary to decrease the minimum spacing between adjacent surface features of the photoresist pattern used as an etching mask in forming such fine patterns beyond the resolution limits of presently available photolithographic equipment. The present invention fulfills this need.